EP2S180F1020C4 Datasheet, PDF (675/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Remote System Upgrades with Stratix II and Stratix II GX Devices
Figure 8–6. Remote System Upgrade Circuit Data Path
Status Register (SR)
Bit [4..0]
Control Register
Bit [20..0]
Logic
Update Register
Bit [20..0] _update
Shift Register
dout _{Bit [4..0]}
din dout
capture
Bit [20..0]
din
capture
Internal Oscillator
RSU
State
Machine
timeout
User
Watchdog
Timer
clkout capture update
Logic
clkin
RU_DOUT
RU_SHIFTnLD RU_CAPTnUPDT
RU_CLK RU_DIN RU_nCONFIG RU_nRSTIMER
Logic Array
Remote System Upgrade Registers
The remote system upgrade block contains a series of registers that store
the page addresses, watchdog timer settings, and status information.
These registers are detailed in Table 8–3.
Table 8–3. Remote System Upgrade Registers (Part 1 of 2)
Register
Shift register
Control register
Description
This register is accessible by the logic array and allows the update, status, and control
registers to be written and sampled by user logic. Write access is enabled in remote update
mode for factory configurations to allow writes to the update register. Write access is
disabled in local update mode and for all application configurations in remote update mode.
This register contains the current page address, the user watchdog timer settings, and one
bit specifying whether the current configuration is a factory configuration or an application
configuration. During a read operation in an application configuration, this register is read
into the shift register. When a reconfiguration cycle is initiated, the contents of the update
register are written into the control register.
Altera Corporation
January 2008
8–15
Stratix II Device Handbook, Volume 2