EP2S180F1020C4 Datasheet, PDF (563/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Configuring Stratix II and Stratix II GX Devices
Table 7–5. Pins Affected by the Voltage Level at VCCSEL
Pin
VCCSEL = LOW (connected to GND) VCCSEL = HIGH (connected to V_CCPD)
nSTATUS (when used as an
input)
nCONFIG
CONF_DONE (when used as an
input)
DATA[7..0]
nCE
DCLK (when used as an input)
CS
nWS
nRS
3.3/2.5-V input buffer is selected.
Input buffer is powered by V_{C C P D} .
1.8/1.5-V input buffer is selected.
Input buffer is powered by V_{C C I O} of
the I/O bank. These input buffers are
3.3 V tolerant.
nCS
CLKUSR
DEV_OE
DEV_CLRn
RUnLU
PLL_ENA
VCCSEL is sampled during power-up. Therefore, the VCCSEL setting
cannot change on the fly or during a reconfiguration. The VCCSEL input
buffer is powered by V_CCINT and has an internal 5-kpull-down resistor
that is always active.
1 VCCSEL must be hardwired to V_CCPD or GND.
A logic high selects the 1.8-V/1.5-V input buffer, and a logic low selects
the 3.3-V/2.5-V input buffer. VCCSEL should be set to comply with the
logic levels driven out of the configuration device or MAX II device or a
microprocessor with flash memory.
VCCSEL also sets the POR trip point for I/O bank 3 to ensure that this I/O
bank has powered up to the appropriate voltage levels before
configuration begins. For passive serial (PS) mode (MSEL[3..0] = 0010)
and for Fast passive parallel (FPP) mode (MSEL[3..0] = 0000) the POR
circuitry selects the trip point associated with 1.5-V/1.8-V signaling. For
all other configuration modes defined by MSEL[3..0] settings (other
Altera Corporation
January 2008
7–11
Stratix II Device Handbook, Volume 2