EP2S180F1020C4 Datasheet, PDF (376/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Memory Modes
The widest bit configuration of the M4K and M-RAM blocks in true dual-
port mode is as follows:
■ 256 × 16-bit (×18-bit with parity) (M4K)
■ 8K × 64-bit (×72-bit with parity) (M-RAM)
The 128 × 32-bit (×36-bit with parity) configuration of the M4K block and
the 4K × 128-bit (×144-bit with parity) configuration of the M-RAM block
are unavailable because the number of output drivers is equivalent to the
maximum bit width of the respective memory block. Because true
dual-port RAM has outputs on two ports, the maximum width of the true
dual-port RAM equals half of the total number of output drivers.
Table 2–12 lists the possible M4K block mixed-port width configurations.
Table 2–12. Stratix II and Stratix II GX M4K Block Mixed-Port Width Configurations (True Dual-Port)
Read Port
4K × 1
2K × 2
1K × 4
512 × 8
256 × 16
512 × 9
256 × 18
4K × 1
v
v
v
v
v
2K × 2
v
v
v
v
v
Write Port
1K × 4
v
v
v
v
v
512 × 8
v
v
v
v
v
256 × 16
v
v
v
v
v
512 × 9
v
v
256 × 18
v
v
Table 2–13 lists the possible M-RAM block mixed-port width
configurations.
Table 2–13. Stratix II and Stratix II GX M-RAM Block Mixed-Port Width
Configurations (True Dual-Port)
Read Port
64K × 9
32K × 18
18K × 36
8K × 72
64K × 9
v
v
v
v
Write Port
32K × 18 18K × 36
v
v
v
v
v
v
v
v
8K × 72
v
v
v
v
2–16
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008