EP2S180F1020C4 Datasheet, PDF (331/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

PLLs in Stratix II and Stratix II GX Devices
Table 1–18 shows the connection of the clock pins to the global clock
resources. The reason for the higher level of connectivity is to support
user controllable global clock multiplexing.
Table 1–18. Clock Input Pin Connectivity to Global Clock Networks
CLK(p) (Pin)
Clock Resource
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
GCLK0
vv
GCLK1
vv
GCLK2
vv
GCLK3
vv
GCLK4
vv
GCLK5
vv
GCLK6
vv
GCLK7
vv
GCLK8
vv
(1) (1)
GCLK9
vv
(1) (1)
GCLK10
vv
(1) (1)
GCLK11
vv
(1) (1)
GCLK12
vv
GCLK13
vv
GCLK14
vv
GCLK15
vv
Note to Table 1–18:
(1) Clock pins 8, 9, 10, and 11 are not available in Stratix II GX devices. Therefore, these connections do not exist in
Stratix II GX devices.
Altera Corporation
July 2009
1–67
Stratix II Device Handbook, Volume 2