EP2S180F1020C4 Datasheet, PDF (503/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

High-Speed Differential I/O Interfaces with DPA in Stratix II and Stratix II GX Devices
Table 5–4 shows the conventions for differential bit naming for
18 differential channels. The MSB and LSB positions increase with the
number of channels used in a system.
Table 5–4. LVDS Bit Naming
Receiver Channel Data
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Internal 8-Bit Parallel Data
MSB Position
LSB Position
7
0
15
8
23
16
31
24
39
32
47
40
55
48
63
56
71
64
79
72
87
80
95
88
103
96
111
104
119
112
127
120
135
128
143
136
Receiver Skew Margin for Non-DPA
Changes in system environment, such as temperature, media (cable,
connector, or PCB) loading effect, the receiver's setup and hold times, and
internal skew, reduce the sampling window for the receiver. The timing
margin between the receiver’s clock input and the data input sampling
window is called Receiver Skew Margin (RSKM). Figure 5–19 shows the
relationship between the RSKM and the receiver’s sampling window.
Altera Corporation
January 2008
5–19
Stratix II Device Handbook, Volume 2