EP2S180F1020C4 Datasheet, PDF (414/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Stratix II and Stratix II GX DDR Memory Support Overview
The DQS pins are listed in the Stratix II or Stratix II GX pin tables as
DQS[17..0]T or DQS[17..0]B. The T denotes pins on the top of the
device and the B denotes pins on the bottom of the device. The
complement DQSn pins are marked as DQSn[17..0]T or
DQSn[17..0]B. The corresponding DQ pins are marked as
DQ[17..0]T[3..0], where [17..0] indicates which DQS group the
pins belong to. Similarly, the corresponding DQVLD pins are marked as
DQVLD[8..0]T, where [8..0] indicates which DQS group the pins
belong to. The numbering scheme starts from right to left on the package
bottom view. When not used as DQ, DQS, or DQSn pins, these pins are
available as regular I/O pins. Figure 3–7 shows the DQS pins in Stratix II
or Stratix II GX I/O banks.
1
The Quartus II software treats DQVLD pins as regular DQ pins.
Therefore, you must ensure that the DQVLD pin assigned in
your design corresponds to the pin table’s recommended
DQVLD pins.
Figure 3–7. DQS Pins in Stratix II and Stratix II GX I/O Banks
Up to 8 Sets of
DQ & DQS Pins
Notes (1), (2), (3)
Up to 10 Sets of
DQ & DQS Pins
DQ
Pins
DQ
Pins
I/O
Bank 3
PLL 11
I/O
Bank 11
PLL 5
I/O
Bank 9
DQS
Phase
Shift
Circuitry
I/O
Bank 4
DQSn
Pin
DQS
Pin
DQSn
Pin
DQS
Pin
Notes to Figure 3–7:
(1) There are up to 18 pairs of DQS and DQSn pins on both the top and bottom of the device. See Table 3–3 for the exact
number of DQS and DQSn pin pairs in each device package.
(2) See Table 3–7 for the available DQS and DQSn pins in each mode and package.
(3) Each DQS pin has a complement DQSn pin. DQS and DQSn pins are not differential.
The DQ pin numbering is based on ×4 mode. There are up to 8 DQS/DQ
groups in ×4 mode in I/O banks 3 and 8 and up to 10 DQS/DQ groups in
×4 mode in I/O banks 4 and 7. In ×8/×9 mode, two adjacent ×4 DQS/DQ
groups plus one parity pin are combined; one pair of DQS/DQSn pins
from the combined groups can drive all the DQ and parity pins. Since
there is an even number of DQS/DQ groups in an I/O bank, combining
groups is efficient. Similarly, in ×16/×18 mode, four adjacent ×4 DQS/DQ
groups plus two parity pins are combined and one pair of DQS/DQSn
pins from the combined groups can drive all the DQ and parity pins. In
3–18
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008