EP2S180F1020C4 Datasheet, PDF (471/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Selectable I/O Standards in Stratix II and Stratix II GX Devices
f
1 On-chip parallel termination with calibration is only supported
for input pins. Pins configured as bidirectional do not support
on-chip parallel termination.
The RUP and RDN pins are dual-purpose I/Os, which means they can be
used as regular I/Os if the calibration circuit is not used. When used for
calibration, the RUP pin is connected to V_CCIO through an external 25- or
50- resistor for an on-chip series termination value of 25  or 50 ,
respectively. The RDN pin is connected to GND through an external 25-
or 50- resistor for an on-chip series termination value of 25  or 50 ,
respectively. For on-chip parallel termination, the RUP pin is connected to
V_CCIO through an external 50- resistor, and RDN is connected to GND
through an external 50- resistor.
For more information on tolerance specifications for on-chip termination
with calibration, refer to the DC & Switching Characteristics chapter in
volume 1 of the Stratix II Device Handbook or the DC & Switching
Characteristics chapter in volume 1 of the Stratix II GX Device Handbook.
Design
Considerations
While Stratix II and Stratix II GX devices feature various I/O capabilities
for high-performance and high-speed system designs, there are several
other considerations that require attention to ensure the success of those
designs.
I/O Termination
I/O termination requirements for single-ended and differential I/O
standards are discussed in this section.
Single-Ended I/O Standards
Although single-ended, non-voltage-referenced I/O standards do not
require termination, impedance matching is necessary to reduce
reflections and improve signal integrity.
Voltage-referenced I/O standards require both an input reference
voltage, V_REF, and a termination voltage, V_TT. The reference voltage of the
receiving device tracks the termination voltage of the transmitting device.
Each voltage-referenced I/O standard requires a unique termination
setup. For example, a proper resistive signal termination scheme is critical
in SSTL standards to produce a reliable DDR memory system with
superior noise margin.
Altera Corporation
January 2008
4–33
Stratix II Device Handbook, Volume 2