EP2S180F1020C4 Datasheet, PDF (568/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Fast Passive Parallel Configuration
f
Upon power-up, the Stratix II and Stratix II GX devices go through a
Power-On Reset (POR). The POR delay is dependent on the PORSEL pin
setting; when PORSEL is driven low, the POR time is approximately
100 ms, if PORSEL is driven high, the POR time is approximately 12 ms.
During POR, the device resets, holds nSTATUS low, and tri-states all user
I/O pins. Once the device successfully exits POR, all user I/O pins
continue to be tri-stated. If nIO_pullup is driven low during power-up
and configuration, the user I/O pins and dual-purpose I/O pins have
weak pull-up resistors, which are on (after POR) before and during
configuration. If nIO_pullup is driven high, the weak pull-up resistors
are disabled.
1 You can hold nConfig low in order to stop device
configuration.
The value of the weak pull-up resistors on the I/O pins that are on before
and during configuration can be found in the DC & Switching
Characteristics chapter in volume 1 of the Stratix II Device Handbook or the
DC & Switching Characteristics chapter in volume 1 of the Stratix II GX
Device Handbook.
The configuration cycle consists of three stages: reset, configuration and
initialization. While nCONFIG or nSTATUS are low, the device is in the
reset stage. To initiate configuration, the MAX II device must drive the
nCONFIG pin from low-to-high.
1
V_CCINT, V_CCIO, and V_CCPD of the banks where the configuration
and JTAG pins reside need to be fully powered to the
appropriate voltage levels in order to begin the configuration
process.
When nCONFIG goes high, the device comes out of reset and releases the
open-drain nSTATUS pin, which is then pulled high by an external 10-k
pull-up resistor. Once nSTATUS is released, the device is ready to receive
configuration data and the configuration stage begins. When nSTATUS is
pulled high, the MAX II device places the configuration data one byte at
a time on the DATA[7..0] pins.
1
Stratix II and Stratix II GX devices receive configuration data on
the DATA[7..0] pins and the clock is received on the DCLK pin.
Data is latched into the device on the rising edge of DCLK. If you
are using the Stratix II or Stratix II GX decompression and/or
design security feature, configuration data is latched on the
rising edge of every fourth DCLK cycle. After the configuration
data is latched in, it is processed during the following three
DCLK cycles.
7–16
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008