EP2S180F1020C4 Datasheet, PDF (606/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Passive Serial Configuration
Table 7–15. PS Timing Parameters for Stratix II and Stratix II GX Devices (Part 2 of 2)
Symbol
Parameter
Min
t_CFG
nCONFIG low pulse width
2
t_STATUS nSTATUS low pulse width
10
t_CF2ST1 nCONFIG high to nSTATUS high
t_CF2CK nCONFIG high to first rising edge on DCLK
100
t_ST2CK nSTATUS high to first rising edge of DCLK
2
t_DSU
Data setup time before rising edge on DCLK
5
t_DH
Data hold time after rising edge on DCLK
0
t_CH
DCLK high time
4
t_CL
DCLK low time
4
t_CLK
DCLK period
10
f_MAX
DCLK frequency
t_R
Input rise time
t_F
Input fall time
t_CD2UM CONF_DONE high to user mode (2)
20
t_{C D2 CU} CONF_DONE high to CLKUSR enabled
4  maximum
DCLK period
t_{C D 2 U M C} CONF_DONE high to user mode with
CLKUSR option on
t_{C D 2 C U} + (299 
CLKUSR period)
Max
100 (1)
100 (1)
100
40
40
100
Units
µs
µs
µs
µs
µs
ns
ns
ns
ns
ns
MHz
ns
ns
µs
Notes to Table 7–15:
(1) This value is applicable if users do not delay configuration by extending the nCONFIG or nSTATUS low pulse
width.
(2) The minimum and maximum numbers apply only if the internal oscillator is chosen as the clock source for starting
the device.
f
Device configuration options and how to create configuration files are
discussed further in Software Settings in volume 2 of the Configuration
Handbook.
An example PS design that uses a MAX II device as the external host for
configuration will be available when devices are available.
PS Configuration Using a Microprocessor
In the PS configuration scheme, a microprocessor can control the transfer
of configuration data from a storage device, such as flash memory, to the
target Stratix II or Stratix II GX device.
7–54
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008