EP2S180F1020C4 Datasheet, PDF (241/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

DC & Switching Characteristics
Table 5–97. DQS Phase Jitter Specifications for DLL-Delayed Clock
(tDQS PHASE_JITTER) Note (1)
Number of DQS Delay
Buffer Stages (2)
DQS Phase Jitter
Unit
1
30
ps
2
60
ps
3
90
ps
4
120
ps
Notes to Table 5–97:
(1) Peak-to-peak phase jitter on the phase shifted DDS clock (digital jitter is caused
by DLL tracking).
(2) Delay stages used for requested DQS phase shift are reported in your project’s
Compilation Report in the Quartus II software.
Table 5–98. DQS Phase-Shift Error Specifications for DLL-Delayed Clock (tDQS_PSERR) (1)
Number of DQS Delay Buffer Stages (2) –3 Speed Grade –4 Speed Grade –5 Speed Grade Unit
1
25
30
35
ps
2
50
60
70
ps
3
75
90
105
ps
4
100
120
140
ps
Notes to Table 5–98:
(1) This error specification is the absolute maximum and minimum error. For example, skew on three delay buffer
stages in a C3 speed grade is 75 ps or ± 37.5 ps.
(2) Delay stages used for requested DQS phase shift are reported in your project’s Compilation Report in the
Quartus II software.
Table 5–99. DQS Bus Clock Skew Adder Specifications
(tDQS_CLOCK_SKEW_ADDER)
Mode
DQS Clock Skew Adder
Unit
×4 DQ per DQS
40
ps
×9 DQ per DQS
70
ps
×18 DQ per DQS
75
ps
×36 DQ per DQS
95
ps
Note to Table 5–99:
(1) This skew specification is the absolute maximum and minimum skew. For
example, skew on a ×4 DQ group is 40 ps or ±20 ps.
Altera Corporation
April 2011
5–95
Stratix II Device Handbook, Volume 1