EP2S180F1020C4 Datasheet, PDF (461/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Selectable I/O Standards in Stratix II and Stratix II GX Devices
Table 4–2. Stratix II and Stratix II GX Regular I/O Standards Support (Part 2 of 2)
I/O Standard
General I/O Bank
Enhanced PLL External
Clock Output Bank (2)
1 2 3 4 5(1) 6(1) 7 8 9 10 11 12
SSTL-18 Class I
v v v v vvvvv v v v
SSTL-18 Class II
(3) (3) _{v v} (3) (3) _{v v v v v v}
1.8-V HSTL Class I
v v _{v v} vvvvv _{v v v}
1.8-V HSTL Class II
(3) (3) _{v v} (3) (3) _{v v v v v v}
1.5-V HSTL Class I
v v v v vvvvv v v v
1.5-V HSTL Class II
(3) (3) _{v v} (3) (3) _{v v v v v v}
1.2-V HSTL
v
vv
Differential SSTL-2 Class I
(4) (4) (5) (5) (4) (4) (5) (5)
Differential SSTL-2 Class II
(4) (4) (5) (5) (4) (4) (5) (5)
Differential SSTL-18 Class I
(4) (4) (5) (5) (4) (4) (5) (5)
Differential SSTL-18 Class II (4) (4) (5) (5) (4) (4) (5) (5)
1.8-V differential HSTL Class I (4) (4) (5) (5) (4) (4) (5) (5)
1.8-V differential HSTL Class II (4) (4) (5) (5) (4) (4) (5) (5)
1.5-V differential HSTL Class I (4) (4) (5) (5) (4) (4) (5) (5)
1.5-V differential HSTL Class II (4) (4) (5) (5) (4) (4) (5) (5)
LVDS
v v ^{(6) (6)} v v ^{(6) (6)} v v v v
HyperTransport technology
vv
vv
Differential LVPECL
(6) (6)
(6) (6) _{v v v v}
Notes to Table 4–2:
(1) This bank is not available in Stratix II GX Devices.
(2) A mixture of single-ended and differential I/O standards is not allowed in enhanced PLL external clock output
bank.
(3) This I/O standard is only supported for the input operation in this I/O bank.
(4) Although the Quartus II software does not support pseudo-differential SSTL/HSTL I/O standards on the left and
right I/O banks, you can implement these standards at these banks. Refer to the “Differential I/O Standards” on
page 4–10 for details.
(5) This I/O standard is supported for both input and output operations for pins that support the DQS function. Refer
to the “Differential I/O Standards” on page 4–10 for details.
(6) This I/O standard is only supported for the input operation for pins that support PLL INCLK function in this I/O
bank.
Altera Corporation
January 2008
4–23
Stratix II Device Handbook, Volume 2