Z8F4822AR020SG Datasheet, PDF (98/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
78
Bit
[7]
TEN
[6]
TPOL
Description
Timer Enable
0 = Timer is disabled.
1 = Timer enabled to count.
Timer Input/Output Polarity
Operation of this bit is a function of the current operating mode of the timer.
ONE-SHOT Mode
When the timer is disabled, the timer output signal is set to the value of this bit. When the timer
is enabled, the timer output signal is complemented upon timer reload.
CONTINUOUS Mode
When the timer is disabled, the timer output signal is set to the value of this bit. When the timer
is enabled, the timer output signal is complemented upon timer reload.
COUNTER Mode
When the timer is disabled, the timer output signal is set to the value of this bit. When the timer
is enabled, the timer output signal is complemented upon timer reload.
0 = Count occurs on the rising edge of the timer input signal.
1 = Count occurs on the falling edge of the timer input signal.
PWM Mode
0 = timer output is forced Low (0) when the timer is disabled. When enabled, the timer output is
forced High (1) upon PWM count match and forced Low (0) upon reload.
1 = timer output is forced High (1) when the timer is disabled. When enabled, the timer output
is forced Low (0) upon PWM count match and forced High (1) upon reload.
CAPTURE Mode
0 = Count is captured on the rising edge of the timer input signal.
1 = Count is captured on the falling edge of the timer input signal.
COMPARE Mode
When the timer is disabled, the timer output signal is set to the value of this bit. When the timer
is enabled, the timer output signal is complemented upon timer reload.
GATED Mode
0 = Timer counts when the timer input signal is High (1) and interrupts are generated on the
falling edge of the timer input.
1 = Timer counts when the timer input signal is Low (0) and interrupts are generated on the ris-
ing edge of the timer input.
CAPTURE/COMPARE Mode
0 = Counting is started on the first rising edge of the timer input signal. The current count is
captured on subsequent rising edges of the timer input signal.
1 = Counting is started on the first falling edge of the timer input signal. The current count is
captured on subsequent falling edges of the timer input signal.
Caution: When the timer output alternate function TxOUT on a GPIO port pin is enabled,
TxOUT will change to whatever state the TPOL bit is in. The timer does not need to be enabled
for that to happen. Also, the Port Data Direction Subregister is not needed to be set to output
on TxOUT. Changing the TPOL bit with the timer enabled and running does not immediately
change the TxOUT.
PS019924-0113
PRELIMINARY
Timer Control Register Definitions