Z8F4822AR020SG Datasheet, PDF (80/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
60
Interrupt Edge Select Register
The Interrupt Edge Select (IRQES) Register, shown in Table 36, determines whether an
interrupt is generated for the rising edge or falling edge on the selected GPIO port input
pin. The Interrupt Port Select Register selects between Port A and Port D for the individ-
ual interrupts.
Table 36. Interrupt Edge Select Register (IRQES)
Bit
Field
RESET
R/W
Address
7
IES7
6
IES6
5
IES5
4
3
IES4
IES3
0
R/W
FCDH
2
IES2
1
IES1
0
IES0
Bit
Description
[7:0]
IESx
Interrupt Edge Select x
The minimum pulse width should be greater than 1 system clock to guarantee capture of the
edge triggered interrupt. Shorter pulses may be captured but not guaranteed.
0 = An interrupt request is generated on the falling edge of the PAx/PDx input.
1 = An interrupt request is generated on the rising edge of the PAx/PDx input.
Note: x indicates specific GPIO port pins in the range [7:0].
Interrupt Port Select Register
The Port Select (IRQPS) Register, shown in Table 37, determines the port pin that gener-
ates the PAx/PDx interrupts. This register allows either Port A or Port D pins to be used as
interrupts. The Interrupt Edge Select Register controls the active interrupt edge.
Table 37. Interrupt Port Select Register (IRQPS)
Bit
Field
RESET
R/W
Address
7
PAD7S
6
PAD6S
5
PAD5S
4
3
PAD4S PAD3S
0
R/W
FCEH
2
PAD2S
1
PAD1S
0
PAD0S
Bit
Description
[7:0]
PADxS
PAx/PDx Selection
0 = PAx is used for the interrupt for PAx/PDx interrupt request.
1 = PDx is used for the interrupt for PAx/PDx interrupt request.
Note: x indicates specific GPIO port pins in the range [7:0].
PS019924-0113
PRELIMINARY
Interrupt Control Register Definitions