Z8F4822AR020SG Datasheet, PDF (78/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
58
IRQ2 Enable High and Low Bit Registers
Table 33 describes the priority control for IRQ2. The IRQ2 Enable High and Low Bit reg-
isters, shown in Tables 34 and 35, form a priority-encoded enabling for interrupts in the
Interrupt Request 2 Register. Priority is generated by setting bits in each register.
Table 33. IRQ2 Enable and Priority Encoding
IRQ2ENH[x]
IRQ2ENL[x]
Priority
0
0
Disabled
0
1
Level 1
1
0
Level 2
1
1
Level 3
Note: x indicates register bits in the range [7:0].
Description
Disabled
Low
Nominal
High
Table 34. IRQ2 Enable High Bit Register (IRQ2ENH)
Bit
Field
RESET
R/W
Address
7
T3ENH
6
U1RENH
5
U1TENH
4
3
DMAENH C3ENH
0
R/W
FC7H
2
C2ENH
1
C1ENH
0
C0ENH
Bit
Description
[7]
Timer 3 Interrupt Request Enable High Bit
T3ENH
[6]
UART 1 Receive Interrupt Request Enable High Bit
U1RENH
[5]
UART 1 Transmit Interrupt Request Enable High Bit
U1TENH
[4]
DMA Interrupt Request Enable High Bit
DMAENH
[3]
Port C3 Interrupt Request Enable High Bit
C3ENH
[2]
Port C2 Interrupt Request Enable High Bit
C2ENH
[1]
Port C1 Interrupt Request Enable High Bit
C1ENH
[0]
Port C0 Interrupt Request Enable High Bit
C0ENH
PS019924-0113
PRELIMINARY
Interrupt Control Register Definitions