Z8F4822AR020SG Datasheet, PDF (52/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
32
Watchdog Timer Reset
If the device is in normal or HALT Mode, the Watchdog Timer can initiate a system reset
at time-out if the WDT_RES option bit is set to 1. This capability is the default 
(unprogrammed) setting of the WDT_RES option bit. The WDT status bit in the WDT
Control Register is set to signify that the reset was initiated by the Watchdog Timer.
External Pin Reset
The RESET pin has a Schmitt-triggered input, an internal pull-up, an analog filter and a
digital filter to reject noise. Once the RESET pin is asserted for at least 4 system clock
cycles, the devices progress through the system reset sequence. While the RESET input
pin is asserted Low, the Z8 Encore! XP F64xx Series devices continue to be held in the
Reset state. If the RESET pin is held Low beyond the system reset time-out, the devices
exit the Reset state immediately following RESET pin deassertion. Following a system
reset initiated by the external RESET pin, the EXT status bit in the Watchdog Timer Con-
trol (WDTCTL) Register is set to 1.
On-Chip Debugger Initiated Reset
A Power-On Reset can be initiated using the On-Chip Debugger by setting the RST bit in
the OCD Control Register. The On-Chip Debugger block is not reset but the rest of the
chip goes through a normal system reset. The RST bit automatically clears during the sys-
tem reset. Following the system reset the POR bit in the WDT Control Register is set.
Stop Mode Recovery
STOP Mode is entered by the eZ8 executing a stop instruction. For detailed STOP Mode
information, see the Low-Power Modes chapter on page 34. During Stop Mode Recovery,
the devices are held in reset for 66 cycles of the Watchdog Timer oscillator followed by 16
cycles of the system clock. Stop Mode Recovery only affects the contents of the Watchdog
Timer Control Register. Stop Mode Recovery does not affect any other values in the Reg-
ister File, including the Stack Pointer, Register Pointer, Flags, peripheral control registers,
and general-purpose RAM.
The eZ8 CPU fetches the Reset vector at program memory addresses 0002H and 0003H
and loads that value into the Program Counter. Program execution begins at the Reset vec-
tor address. Following Stop Mode Recovery, the stop bit in the Watchdog Timer Control
Register is set to 1. Table 10 lists the Stop Mode Recovery sources and resulting actions.
PS019924-0113
PRELIMINARY
Stop Mode Recovery