Z8F4822AR020SG Datasheet, PDF (170/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
150
Direct Memory Access Controller
The Z8 Encore! XP F64xx Series Direct Memory Access (DMA) Controller provides
three independent Direct Memory Access channels. Two of the channels, DMA0 and
DMA1, transfer data between the on-chip peripherals and the Register File. The third
channel, DMA_ADC, controls the ADC operation and transfers SINGLE-SHOT Mode
ADC output data to the Register File.
Operation
DMA0 and DMA1, referred to collectively as DMAx, transfer data either from the on-chip
peripheral control registers to the Register File, or from the Register File to the on-chip
peripheral control registers. The sequence of operations in a DMAx data transfer is:
1. DMAx trigger source requests a DMA data transfer.
2. DMAx requests control of the system bus (address and data) from the eZ8 CPU.
3. After the eZ8 CPU acknowledges the bus request, DMAx transfers either a single byte
or a two-byte word (depending upon configuration) and then returns system bus con-
trol to the eZ8 CPU.
4. If the Current Address equals the End Address, then the following conditions are true:
– DMAx reloads the original Start Address
– If configured to generate an interrupt, DMAx sends an interrupt request to the
Interrupt Controller
– If configured for single-pass operation, DMAx resets the DEN bit in the DMAx
Control Register to 0 and the DMA is disabled
If the Current Address does not equal the End Address, then the Current Address
increments by 1 (single-byte transfer) or 2 (two-byte word transfer).
Configuring DMA0 and DMA1 for Data Transfer
Observe the following procedure to configure and enable DMA0 or DMA1:
1. Write to the DMAx I/O Address Register to set the Register File address identifying
the on-chip peripheral control register. The upper nibble of the 12-bit address for on-
chip peripheral control registers is always FH. The full address is {FH,
DMAx_IO[7:0]}.
PS019924-0113
PRELIMINARY
Direct Memory Access Controller