Z8F4822AR020SG Datasheet, PDF (144/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
124
Bit
[5]
COL
[4]
ABT
[3:2]
[1]
TXST
[0]
SLAS
Description (Continued)
Collision
0 = A multimaster collision (mode fault) has not occurred.
1 = A multimaster collision (mode fault) has been detected.
Slave Mode Transaction Abort
This bit is set if the SPI is configured in slave mode, a transaction is occurring and SS deas-
serts before all bits of a character have been transferred as defined by the NUMBITS field of
the SPIMODE Register. The IRQ bit also sets, indicating the transaction has completed.
0 = A slave mode transaction abort has not occurred.
1 = A slave mode transaction abort has been detected.
Reserved
These bits are reserved and must be programmed to 00.
Transmit Status
0 = No data transmission currently in progress.
1 = Data transmission currently in progress.
Slave Select
If SPI enabled as a Slave, then the following conditions are true:
0 = SS input pin is asserted (Low).
1 = SS input is not asserted (High).
If SPI enabled as a Master, this bit is not applicable.
PS019924-0113
PRELIMINARY
SPI Control Register Definitions