Z8F4822AR020SG Datasheet, PDF (12/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
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Figure 31. 10-Bit Addressed Slave Data Transfer Format . . . . . . . . . . . . . . . . . . . . . 136
Figure 32. Receive Data Transfer Format for a 7-Bit Addressed Slave . . . . . . . . . . . 138
Figure 33. Receive Data Format for a 10-Bit Addressed Slave . . . . . . . . . . . . . . . . . 139
Figure 34. Analog-to-Digital Converter Block Diagram . . . . . . . . . . . . . . . . . . . . . . 162
Figure 35. Flash Memory Arrangement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Figure 36. On-Chip Debugger Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Figure 37. Interfacing the On-Chip Debugger’s DBG Pin with an RS-232 Interface, 
#1 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Figure 38. Interfacing the On-Chip Debugger’s DBG Pin with an RS-232 Interface, 
#2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Figure 39. OCD Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Figure 40. Recommended 20MHz Crystal Oscillator Configuration . . . . . . . . . . . . . 197
Figure 41. Connecting the On-Chip Oscillator to an External RC Network . . . . . . . . 198
Figure 42. Typical RC Oscillator Frequency as a Function of the External 
Capacitance with a 45 kΩ Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Figure 43. Typical Active Mode Idd vs. System Clock Frequency . . . . . . . . . . . . . . 205
Figure 44. Maximum Active Mode Idd vs. System Clock Frequency . . . . . . . . . . . . 206
Figure 45. Typical HALT Mode Idd vs. System Clock Frequency . . . . . . . . . . . . . . 207
Figure 46. Maximum HALT Mode Icc vs. System Clock Frequency . . . . . . . . . . . . 208
Figure 47. Maximum STOP Mode IDD with VBO Enabled vs. Power Supply 
Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Figure 48. Maximum STOP Mode IDD with VBO Disabled vs. Power Supply 
Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Figure 49. Analog-to-Digital Converter Frequency Response . . . . . . . . . . . . . . . . . . 215
Figure 50. Port Input Sample Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Figure 51. GPIO Port Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Figure 52. On-Chip Debugger Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Figure 53. SPI Master Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Figure 54. SPI Slave Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Figure 55. I²C Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Figure 56. UART Timing with CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Figure 57. UART Timing without CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Figure 58. Flags Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Figure 59. Op Code Map Cell Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Figure 60. First Op Code Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Figure 61. Second Op Code Map after 1FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
PS019924-0113
PRELIMINARY
List of Figures