Z8F4822AR020SG Datasheet, PDF (42/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
22
Register File Address Map
Table 7 provides the address map for the Register File of the Z8 Encore! XP F64xx Series
products. Not all devices and package styles in the Z8 Encore! XP F64xx Series support
Timer 3 and all of the GPIO ports. Consider registers for unimplemented peripherals to be
reserved.
Table 7. Z8 Encore! XP F64xx Series Register File Address Map
Address (Hex) Register Description
General-Purpose RAM
000–EFF
General-Purpose Register File RAM
Timer 0
F00
F01
F02
F03
F04
F05
Timer 0 High Byte
Timer 0 Low Byte
Timer 0 Reload High Byte
Timer 0 Reload Low Byte
Timer 0 PWM High Byte
Timer 0 PWM Low Byte
F06
Timer 0 Control 0
F07
Timer 0 Control 1
Timer 1
F08
Timer 1 High Byte
F09
Timer 1 Low Byte
F0A
Timer 1 Reload High Byte
F0B
Timer 1 Reload Low Byte
F0C
Timer 1 PWM High Byte
F0D
Timer 1 PWM Low Byte
F0E
Timer 1 Control 0
F0F
Timer 1 Control 1
Timer 2
F10
Timer 2 High Byte
F11
Timer 2 Low Byte
F12
Timer 2 Reload High Byte
F13
Timer 2 Reload Low Byte
Note: XX = Undefined.
Mnemonic Reset (Hex)
—
XX
T0H
00
T0L
01
T0RH
FF
T0RL
FF
T0PWMH
00
T0PWML
00
T0CTL0
00
T0CTL1
00
T1H
00
T1L
01
T1RH
FF
T1RL
FF
T1PWMH
00
T1PWML
00
T1CTL0
00
T1CTL1
00
T2H
00
T2L
01
T2RH
FF
T2RL
FF
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PS019924-0113
PRELIMINARY
Register File Address Map