Z8F4822AR020SG Datasheet, PDF (153/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
133
Address Only Transaction with a 7-bit Address
In the situation where software determines if a slave with a 7-bit address is responding
without sending or receiving data, a transaction can be done which only consists of an
address phase. Figure 28 displays this address only transaction to determine if a slave with
a 7-bit address will acknowledge. As an example, this transaction can be used after a write
has been performed to an EEPROM to determine when the EEPROM completes its inter-
nal write operation and is again responding to I²C transactions. If the slave does not
Acknowledge, the transaction can be repeated until the slave does Acknowledge.
S Slave Address
W = 0 A/A P
Figure 28. 7-Bit Address Only Transaction Format
Observe the following procedure for an address only transaction to a 7-bit addressed slave:
1. Software asserts the IEN bit in the I²C Control Register.
2. Software asserts the TXI bit of the I²C Control Register to enable transmit interrupts.
3. The I²C interrupt asserts, because the I²C Data Register is empty (TDRE=1)
4. Software responds to the TDRE bit by writing a 7-bit slave address plus write bit (=0)
to the I²C Data Register. As an alternative this could be a read operation instead of a
write operation.
5. Software sets the start and stop bits of the I²C Control Register and clears the TXI bit.
6. The I²C Controller sends the start condition to the I²C slave.
7. The I²C Controller loads the I²C Shift Register with the contents of the I²C Data Reg-
ister.
8. Software polls the stop bit of the I²C Control Register. Hardware deasserts the stop bit
when the address only transaction is completed.
9. Software checks the ACK bit of the I²C Status Register. If the slave acknowledged,
the ACK bit is = 1. If the slave does not acknowledge, the ACK bit is = 0. The NCKI
interrupt does not occur in the not acknowledge case because the stop bit was set.
Write Transaction with a 7-Bit Address
Figure 29 displays the data transfer format for a 7-bit addressed slave. Shaded regions
indicate data transferred from the I²C Controller to slaves and unshaded regions indicate
data transferred from the slaves to the I²C Controller.
PS019924-0113
PRELIMINARY
Operation