Z8F4822AR020SG Datasheet, PDF (108/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
88
Parity Checker
Receiver Control
with address compare
RxD
Receive Shifter
Receive Data
Register
System Bus
Control Registers
Transmit Data
Register
Status Register
Baud Rate
Generator
Transmit Shift
TxD
Register
Parity Generator
Transmitter Control
CTS
DE
Figure 13. UART Block Diagram
Operation
The UART always transmits and receives data in an 8-bit data format, least significant bit
first. An even or odd parity bit can be optionally added to the data stream. Each character
begins with an active Low start bit and ends with either 1 or 2 active High stop bits.
Figures 14 and 15 display the asynchronous data format employed by the UART without
parity and with parity, respectively.
PS019924-0113
PRELIMINARY
Operation