Z8F4822AR020SG Datasheet, PDF (73/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
53
Interrupt Request 1 Register
The Interrupt Request 1 (IRQ1) Register, shown in Table 25, stores interrupt requests for
both vectored and polled interrupts. When a request is presented to the interrupt controller,
the corresponding bit in the IRQ1 Register becomes 1. If interrupts are globally enabled
(vectored interrupts), the interrupt controller passes an interrupt request to the eZ8 CPU. If
interrupts are globally disabled (polled interrupts), the eZ8 CPU can read the Interrupt
Request 1 Register to determine if any interrupt requests are pending.
For each pin, only 1 of either Port A or Port D can be enabled for interrupts at any one
time. Port selection (A or D) is determined by the values in the Interrupt Port Select Regis-
ter (IRQPS): see page 60.
Table 25. Interrupt Request 1 Register (IRQ1)
Bit
Field
RESET
R/W
Address
7
PAD7I
6
PAD6I
5
PAD5I
4
3
PAD4I PAD3I
0
R/W
FC3H
2
PAD2I
1
PAD1I
0
PAD0I
Bit
Description
[7:0]
PADxI
Port A or Port D Pin x Interrupt Request
0 = No interrupt request is pending for GPIO Port A or Port D pin x.
1 = An interrupt request from GPIO Port A or Port D pin x is awaiting service.
Note: x indicates the specific GPIO Port A or D pin in the range [7:0].
PS019924-0113
PRELIMINARY
Interrupt Control Register Definitions