Z8F4822AR020SG Datasheet, PDF (69/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
49
Architecture
Figure 11 displays a block diagram of the interrupt controller.
Port Interrupts
Internal Interrupts
High
Priority
Medium
Priority
Vector
Priority
Mux
IRQ Request
Low
Priority
Figure 11. Interrupt Controller Block Diagram
Operation
This section describes the operational aspects of the following functions.
Master Interrupt Enable: see page 49
Interrupt Vectors and Priority: see page 50
Interrupt Assertion: see page 50
Software Interrupt Assertion: see page 51
Master Interrupt Enable
The master interrupt enable bit (IRQE) in the Interrupt Control Register globally enables
and disables interrupts.
Interrupts are globally enabled by any of the following actions:
• Executing an Enable Interrupt (EI) instruction
• Executing an Return from Interrupt (IRET) instruction
PS019924-0113
PRELIMINARY
Architecture