Z8F4822AR020SG Datasheet, PDF (243/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
223
UART Timing
Figure 56 and Table 121 provide timing information for UART pins for the case where the
Clear To Send input pin (CTS) is used for flow control. In this example, it is assumed that
the Driver Enable polarity has been configured to be Active Low and is represented here
by DE. The CTS to DE assertion delay (T1) assumes the UART Transmit Data Register
has been loaded with data prior to CTS assertion.
CTS
(Input)
DE
(Output)
TxD
(Output)
T₁
T₂
Start Bit 0 Bit 1
T₃
Bit 7 Parity ^Stop
Figure 56. UART Timing with CTS
End of
Stop Bit(s)
Table 121. UART Timing with CTS
Parameter Abbreviation
T₁
CTS Fall to DE Assertion Delay
T₂
DE Assertion to TxD Falling Edge (Start) Delay
T₃
End of stop bit(s) to DE Deassertion Delay
Delay (ns)
Minimum
2 * X_IN period
1 bit period
1 * X_IN period
Maximum
2 * X_IN period +
1 bit period
1 bit period +
1 * X_IN period
2 * X_IN period
PS019924-0113
PRELIMINARY
AC Characteristics