Z8F4822AR020SG Datasheet, PDF (48/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
28
Reset and Stop Mode Recovery
The Reset Controller within the Z8 Encore! XP F64xx Series controls Reset and Stop
Mode Recovery operation. In typical operation, the following events cause a Reset to
occur:
• Power-On Reset
• Voltage Brown-Out
• Watchdog Timer time-out (when configured via the WDT_RES option bit to initiate a
Reset)
• External RESET pin assertion
• On-Chip Debugger initiated Reset (OCDCTL[0] set to 1)
When the Z8 Encore! XP F64xx Series devices are in STOP Mode, a Stop Mode Recovery
is initiated by either of the following events:
• Watchdog Timer time-out
• GPIO port input pin transition on an enabled Stop Mode Recovery source
• DBG pin driven Low
Reset Types
The Z8 Encore! XP F64xx Series provides two different types of reset operation (system
reset and Stop Mode Recovery). The type of Reset is a function of both the current operat-
ing mode of the Z8 Encore! XP F64xx Series devices and the source of the Reset. Table 8
lists the types of Reset and their operating characteristics.
Table 8. Reset and Stop Mode Recovery Characteristics and Latency
Reset Type
System reset
Stop Mode
Recovery
Reset Characteristics and Latency
Control Registers eZ8 CPU Reset Latency (Delay)
Reset (as applicable) Reset
66 WDT Oscillator cycles + 16 System Clock cycles
Unaffected, except Reset
WDT_CTL Register
66 WDT Oscillator cycles + 16 System Clock cycles
PS019924-0113
PRELIMINARY
Reset and Stop Mode Recovery