Z8F4822AR020SG Datasheet, PDF (154/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
134
S Slave Address
W = 0 A Data A Data A Data A/A P/S
Figure 29. 7-Bit Addressed Slave Data Transfer Format
Observe the following procedure for a transmit operation to a 7-bit addressed slave:
1. Software asserts the IEN bit in the I²C Control Register.
2. Software asserts the TXI bit of the I²C Control Register to enable transmit interrupts.
3. The I²C interrupt asserts, because the I²C Data Register is empty
4. Software responds to the TDRE bit by writing a 7-bit slave address plus write bit (=0)
to the I²C Data Register.
5. Software asserts the start bit of the I²C Control Register.
6. The I²C Controller sends the start condition to the I²C slave.
7. The I²C Controller loads the I²C Shift Register with the contents of the I²C Data Reg-
ister.
8. After one bit of address has been shifted out by the SDA signal, the transmit interrupt
is asserted (TDRE = 1).
9. Software responds by writing the transmit data into the I²C Data Register.
10. The I²C Controller shifts the rest of the address and write bit out by the SDA signal.
11. If the I²C slave sends an acknowledge (by pulling the SDA signal Low) during the
next High period of SCL the I²C Controller sets the ACK bit in the I²C Status Regis-
ter. Continue with Step 12.

If the slave does not acknowledge, the Not Acknowledge interrupt occurs (NCKI bit is
set in the Status Register, ACK bit is cleared). Software responds to the Not Acknowl-
edge interrupt by setting the stop and flush bits and clearing the TXI bit. The I²C Con-
troller sends the stop condition on the bus and clears the stop and NCKI bits. The
transaction is complete (ignore the following steps).
12. The I²C Controller loads the contents of the I²C Shift Register with the contents of the
I²C Data Register.
13. The I²C Controller shifts the data out of using the SDA signal. After the first bit is
sent, the transmit interrupt is asserted.
14. If more bytes remain to be sent, return to Step 9.
15. Software responds by setting the stop bit of the I²C Control Register (or start bit to ini-
tiate a new transaction). In the stop case, software clears the TXI bit of the I²C Control
Register at the same time.
PS019924-0113
PRELIMINARY
Operation