Z8F4822AR020SG Datasheet, PDF (162/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
142
Table 71. I²C Data Register (I2CDATA)
Bit
7
6
5
4
3
2
1
0
Field
DATA
RESET
0
R/W
R/W
Address
F50H
I²C Status Register
The read-only I²C Status Register, shown in Table 72, indicates the status of the I²C Con-
troller.
Table 72. I²C Status Register (I2CSTAT)
Bit
Field
RESET
R/W
Address
7
TDRE
1
6
RDRF
5
ACK
4
3
10B
RD
0
R
F51H
2
1
0
TAS
DSS
NCKI
Bit
[7]
TDRE
[6]
RDRF
Description
Transmit Data Register Empty
When the I²C Controller is enabled, this bit is 1 when the I²C Data Register is empty. When this
bit is set, an interrupt is generated if the TXI bit is set, except when the I²C Controller is shifting
in data during the reception of a byte or when shifting an address and the RD bit is set. This bit
is cleared by writing to the I2CDATA Register.
Receive Data Register Full
This bit is set = 1 when the I²C Controller is enabled and the I²C Controller has received a byte
of data. When asserted, this bit causes the I²C Controller to generate an interrupt. This bit is
cleared by reading the I²C Data Register (unless the read is performed using execution of the
On-Chip Debugger’s Read Register command).
PS019924-0113
PRELIMINARY
I2C Control Register Definitions