Z8F4822AR020SG Datasheet, PDF (178/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
158
Table 84. DMA_ADC Address Register (DMAA_ADDR)
Bit
7
6
5
4
3
2
1
0
Field
DMAA_ADDR
Reserved
RESET
X
R/W
R/W
Address
FBDH
Bit
Description
[7:1]
DMAA_ADDR
DMA_ADC Address
These bits specify the seven most significant bits of the 12-bit Register File addresses
used for storing the ADC output data. The ADC analog input Number defines the five
least significant bits of the Register File address. Full 12-bit address is
{DMAA_ADDR[7:1], 4-bit ADC analog input Number, 0}.
0
Reserved
This bit is reserved and must be programmed to 0.
DMA_ADC Control Register
The DMA_ADC Control Register, shown in Table 85, enables and sets options (DMA
enable and interrupt enable) for ADC operation.
Table 85. DMA_ADC Control Register (DMAACTL)
Bit
7
6
5
4
3
2
1
0
Field
DAEN IRQEN
Reserved
ADC_IN
RESET
0
R/W
R/W
Address
FBEH
Bit
[7]
DAEN
[6]
IRQEN
Description
DMA_ADC Enable
0 = DMA_ADC is disabled and the ADC analog input Number (ADC_IN) is reset to 0.
1 = DMA_ADC is enabled.
Interrupt Enable
0 = DMA_ADC does not generate any interrupts.
1 = DMA_ADC generates an interrupt after transferring data from the last ADC analog input
specified by the ADC_IN field.
PS019924-0113
PRELIMINARY
DMA Control Register Definitions