Z8F4822AR020SG Datasheet, PDF (183/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
163
Operation
This section describes the operational aspects of the ADC’s power-down and conversion
features.
Automatic Power-Down
If the ADC is idle (i.e., no conversions are in progress) for 160 consecutive system clock
cycles, portions of the ADC are automatically powered down. From this powered-down
state, the ADC requires 40 system clock cycles to power up. The ADC powers up when a
conversion is requested using the ADC Control Register.
Single-Shot Conversion
When configured for single-shot conversion, the ADC performs a single analog-to-digital
conversion on the selected analog input channel. After completion of the conversion, the
ADC shuts down. Observe the following procedure for setting up the ADC and initiating a
single-shot conversion:
1. Enable the appropriate analog inputs by configuring the general-purpose I/O pins for
alternate function. This configuration disables the digital input and output drivers.
2. Write to the ADC Control Register to configure the ADC and begin the conversion.
The bit fields in the ADC Control Register can be written simultaneously:
– Write to the ANAIN[3:0] field to select one of the 12 analog input sources
– Clear CONT to 0 to select a single-shot conversion
– Write to the VREF bit to enable or disable the internal voltage reference generator
– Set CEN to 1 to start the conversion
3. CEN remains 1 while the conversion is in progress. A single-shot conversion requires
5129 system clock cycles to complete. If a single-shot conversion is requested from an
ADC powered-down state, the ADC uses 40 additional clock cycles to power up
before beginning the 5129 cycle conversion.
4. When the conversion is complete, the ADC control logic performs the following oper-
ations:
– 10-bit data result written to {ADCD_H[7:0], ADCD_L[7:6]}
– CEN resets to 0 to indicate the conversion is complete
– An interrupt request is sent to the Interrupt Controller
5. If the ADC remains idle for 160 consecutive system clock cycles, it is automatically
powered down.
PS019924-0113
PRELIMINARY
Operation