Z8F4822AR020SG Datasheet, PDF (205/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
185
RS-232 TX
RS-232 RX
RS-232
Transceiver
V_DD
Open-Drain
Buffer
10 kΩ
DBG Pin
Figure 38. Interfacing the On-Chip Debugger’s DBG Pin with an RS-232 Interface, #2 of 2
DEBUG Mode
The operating characteristics of the Z8 Encore! XP F64xx Series devices in DEBUG
Mode are:
• The eZ8 CPU fetch unit stops, idling the eZ8 CPU, unless directed by the OCD to ex-
ecute specific instructions
• The system clock operates unless in STOP Mode
• All enabled on-chip peripherals operate unless in STOP Mode
• Automatically exits HALT Mode
• Constantly refreshes the Watchdog Timer, if enabled
Entering DEBUG Mode
The device enters DEBUG Mode following any of the following operations:
• Writing the DBGMODE bit in the OCD Control Register to 1 using the OCD interface
• eZ8 CPU execution of a breakpoint (BRK) instruction (when enabled)
• If the DBG pin is Low when the device exits Reset, the On-Chip Debugger automati-
cally puts the device into DEBUG Mode
Exiting DEBUG Mode
The device exits DEBUG Mode following any of the following operations:
• Clearing the DBGMODE bit in the OCD Control Register to 0
• Power-On Reset
PS019924-0113
PRELIMINARY
Operation