Z8F4822AR020SG Datasheet, PDF (145/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
125
SPI Mode Register
The SPI Mode Register, shown in Table 67, configures the character bit width and the
direction and value of the SS pin.
Table 67. SPI Mode Register (SPIMODE)
Bit
Field
RESET
R/W
Address
7
6
Reserved
R
5
DIAG
4
3
2
NUMBITS[2:0]
0
R/W
F63H
1
SSIO
0
SSV
Bit
Description
[7:6]
Reserved
These bits are reserved and must be programmed to 00.
[5]
DIAG
Diagnostic Mode Control bit
This bit is for SPI diagnostics. Setting this bit allows the Baud Rate Generator value to be
read using the SPIBRH and SPIBRL Register locations.
0 = Reading SPIBRH, SPIBRL returns the value in the SPIBRH and SPIBRL registers.
1 = Reading SPIBRH returns bits [15:8] of the SPI Baud Rate Generator; and reading
SPIBRL returns bits [7:0] of the SPI Baud Rate Counter. The Baud Rate Counter High
and Low byte values are not buffered.
Caution: Exercise caution if reading the values while the BRG is counting.
[4]
NUMBITS[2:0]
Number of Data Bits Per Character to Transfer
This field contains the number of bits to shift for each character transfer. For information
about valid bit positions when the character length is less than 8 bits, see the SPI Data
Register (SPIDATA) description.
000 = 8 bits.
001 = 1 bit.
010 = 2 bits.
011 = 3 bits.
100 = 4 bits.
101 = 5 bits.
110 = 6 bits.
111 = 7 bits.
[1]
SSIO
Slave Select I/O
0 = SS pin configured as an input.
1 = SS pin configured as an output (Master mode only).
[0]
SSV
Slave Select Value
If SSIO = 1 and SPI is configured as a Master, the following conditions are true:
0 = SS pin driven Low (0).
1 = SS pin driven High (1).
This bit has no effect if SSIO = 0 or if SPI is configured as a Slave.
PS019924-0113
PRELIMINARY
SPI Control Register Definitions