Z8F4822AR020SG Datasheet, PDF (122/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
102
UART Control 0 and Control 1 Registers
The UART Control 0 and Control 1 Registers, shown in Tables 57 and 58, configure the
properties of the UART’s transmit and receive operations. The UART Control registers
must not been written while the UART is enabled.
Table 57. UART Control 0 Register (UxCTL0)
Bit
Field
RESET
R/W
Address
7
TEN
6
REN
5
CTSE
4
3
PEN
PSEL
0
R/W
F42H and F4AH
2
SBRK
1
STOP
0
LBEN
Bit
[7]
TEN
[6]
REN
[5]
CTSE
[4]
PEN
[3]
PSEL
[2]
SBRK
Description
Transmit Enable
This bit enables or disables the transmitter. The enable is also controlled by the CTS signal
and the CTSE bit. If the CTS signal is low and the CTSE bit is 1, the transmitter is enabled.
0 = Transmitter disabled.
1 = Transmitter enabled.
Receive Enable
This bit enables or disables the receiver.
0 = Receiver disabled.
1 = Receiver enabled.
CTS Enable
0 = The CTS signal has no effect on the transmitter.
1 = The UART recognizes the CTS signal as an enable control from the transmitter.
Parity Enable
This bit enables or disables parity. Even or odd is determined by the PSEL bit. It is overridden
by the MPEN bit.
0 = Parity is disabled.
1 = The transmitter sends data with an additional parity bit and the receiver receives an addi-
tional parity bit.
Parity Select
0 = Even parity is transmitted and expected on all received data.
1 = Odd parity is transmitted and expected on all received data.
Send Break
This bit pauses or breaks data transmission. Sending a break interrupts any transmission in
progress, so ensure that the transmitter has finished sending data before setting this bit.
0 = No break is sent.
1 = The output of the transmitter is zero.
PS019924-0113
PRELIMINARY
UART Control Register Definitions