Z8F4822AR020SG Datasheet, PDF (160/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
140
5. After the first bit has been shifted out, a transmit interrupt is asserted.
6. Software responds by writing the lower eight bits of address to the I²C Data Register.
7. The I²C Controller completes shifting of the two address bits and a 0 (write).
8. If the I²C slave acknowledges the first address byte by pulling the SDA signal Low
during the next High period of SCL, the I²C Controller sets the ACK bit in the I²C
Status Register. Continue with Step 9.

If the slave does not acknowledge the first address byte, the I²C Controller sets the
NCKI bit and clears the ACK bit in the I²C Status Register. Software responds to the
Not Acknowledge interrupt by setting the stop and flush bits and clearing the TXI bit.
The I²C Controller sends the stop condition on the bus and clears the stop and NCKI
bits. The transaction is complete (ignore following steps).
9. The I²C Controller loads the I²C Shift Register with the contents of the I²C Data Reg-
ister (second address byte).
10. The I²C Controller shifts out the second address byte. After the first bit is shifted, the
I²C Controller generates a transmit interrupt.
11. Software responds by setting the start bit of the I²C Control Register to generate a
repeated start by clearing the TXI bit.
12. Software responds by writing 11110B followed by the 2-bit slave address and a 1
(read) to the I²C Data Register.
13. If only one byte is to be read, software sets the NAK bit of the I²C Control Register.
14. After the I²C Controller shifts out the 2nd address byte, the I²C slave sends an
acknowledge by pulling the SDA signal Low during the next High period of SCL, the
I²C Controller sets the ACK bit in the I²C Status Register. Continue with Step 15.

If the slave does not acknowledge the second address byte, the I²C Controller sets the
NCKI bit and clears the ACK bit in the I²C Status Register. Software responds to the
Not Acknowledge interrupt by setting the stop and flush bits and clearing the TXI bit.
The I²C Controller sends the stop condition on the bus and clears the stop and NCKI
bits. The transaction is complete (ignore the following steps).
15. The I²C Controller sends the repeated start condition.
16. The I²C Controller loads the I²C Shift Register with the contents of the I²C Data Reg-
ister (third address transfer).
17. The I²C Controller sends 11110B followed by the two most significant bits of the
slave read address and a 1 (read).
18. The I²C slave sends an acknowledge by pulling the SDA signal Low during the next
High period of SCL

PS019924-0113
PRELIMINARY
Operation