Z8F4822AR020SG Datasheet, PDF (66/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
46
Port A–H Input Data Registers
Reading from the Port A–H Input Data registers, shown in Table 21, returns the sampled
values from the corresponding port pins. The Port A–H Input Data registers are read-only.
Table 21. Port A–H Input Data Registers (PxIN)
Bit
Field
RESET
R/W
Address
7
PIN7
6
5
4
3
2
1
PIN6
PIN5
PIN4
PIN3
PIN2
PIN1
X
R
FD2H, FD6H, FDAH, FDEH, FE2H, FE6H, FEAH, FEEH
0
PIN0
Bit
Description
[7:0]
PxIN
Port Input Data
Sampled data from the corresponding port pin input.
0 = Input data is logical 0 (Low).
1 = Input data is logical 1 (High).
Note: x indicates register bits in the range [7:0].
Port A–H Output Data Register
The Port A–H Output Data Register, shown in Table 22, writes output data to the pins.
Table 22. Port A–H Output Data Register (PxOUT)
Bit
Field
RESET
R/W
Address
7
POUT7
6
5
4
3
2
1
POUT6 POUT5 POUT4 POUT3 POUT2 POUT1
0
R/W
FD3H, FD7H, FDBH, FDFH, FE3H, FE7H, FEBH, FEFH
0
POUT0
Bit
Description
[7:0]
PxOUT
Port Output Data
These bits contain the data to be driven out from the port pins. The values are only driven if the
corresponding pin is configured as an output and the pin is not configured for alternate function
operation.
0 = Drive a logical 0 (Low).
1 = Drive a logical 1 (High). High value is not driven if the drain has been disabled by setting
the corresponding Port Output Control Register bit to 1.
Note: x indicates register bits in the range [7:0].
PS019924-0113
PRELIMINARY
GPIO Control Register Definitions