Z8F4822AR020SG Datasheet, PDF (142/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
122
Table 64. SPI Data Register (SPIDATA)
Bit
7
6
5
4
3
2
1
0
Field
DATA
RESET
X
R/W
R/W
Address
F60H
Bit
[7:0]
DATA
Description
Data
Transmit and/or receive data.
SPI Control Register
The SPI Control Register, shown in Table 65, configures the SPI for transmit and receive
operations.
Table 65. SPI Control Register (SPICTL)
Bit
Field
RESET
R/W
Address
7
IRQE
6
STR
5
BIRQ
4
3
PHASE CLKPOL
0
R/W
F61H
2
WOR
1
MMEN
0
SPIEN
Bit
[7]
IRQE
[6]
STR
[5]
BIRQ
Description
Interrupt Request Enable
0 = SPI interrupts are disabled. No interrupt requests are sent to the Interrupt Controller.
1 = SPI interrupts are enabled. Interrupt requests are sent to the Interrupt Controller.
Start an SPI Interrupt Request
0 = No effect.
1 = Setting this bit to 1 also sets the IRQ bit in the SPI Status Register to 1. Setting this bit
forces the SPI to send an interrupt request to the Interrupt Control. This bit can be used by
software for a function similar to transmit buffer empty in a UART. Writing a 1 to the IRQ bit
in the SPI Status Register clears this bit to 0.
BRG Timer Interrupt Request
If the SPI is enabled, this bit has no effect. If the SPI is disabled:
0 = The Baud Rate Generator timer function is disabled.
1 = The Baud Rate Generator timer function and time-out interrupt are enabled.
PS019924-0113
PRELIMINARY
SPI Control Register Definitions