Z8F4822AR020SG Datasheet, PDF (141/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
121
When configured as a general purpose timer, the interrupt interval is calculated using the
following equation:
Interrupt Interval (s) = System Clock Period (s)  BRG[15:0]
SPI Control Register Definitions
This section defines the features of the following Serial Peripheral Interface registers.
SPI Data Register: see page 121
SPI Control Register: see page 122
SPI Status Register: see page 123
SPI Mode Register: see page 125
SPI Diagnostic State Register: see page 126
SPI Baud Rate High and Low Byte Registers: see page 126
SPI Data Register
The SPI Data Register, shown in Table 64, stores both the outgoing (transmit) data and the
incoming (receive) data. Reads from the SPI Data Register always return the current con-
tents of the 8-bit shift register. Data is shifted out starting with bit 7. The last bit received
resides in bit position 0.
With the SPI configured as a Master, writing a data byte to this register initiates the data
transmission. With the SPI configured as a Slave, writing a data byte to this register loads
the shift register in preparation for the next data transfer with the external Master. In either
the Master or Slave modes, if a transmission is already in progress, writes to this register
are ignored and the overrun error flag, OVR, is set in the SPI Status Register.
When the character length is less than 8 bits (as set by the NUMBITS field in the SPI
Mode Register), the transmit character must be left justified in the SPI Data Register. A
received character of less than 8 bits is right justified (last bit received is in bit position 0).
For example, if the SPI is configured for 4-bit characters, the transmit characters must be
written to SPIDATA[7:4] and the received characters are read from SPIDATA[3:0].
PS019924-0113
PRELIMINARY
SPI Control Register Definitions