Z8F4822AR020SG Datasheet, PDF (105/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
85
Table 49. Watchdog Timer Events
Reset or Stop Mode Recovery Event
POR STOP WDT EXT
Power-On Reset
1
0
0
0
Reset using RESET pin assertion
0
0
0
1
Reset using Watchdog Timer time-out
0
0
1
0
Reset using the On-Chip Debugger (OCDCTL[1] set to 1)
1
0
0
0
Reset from STOP Mode using DBG Pin driven Low
1
0
0
0
Stop Mode Recovery using GPIO pin transition
0
1
0
0
Stop Mode Recovery using Watchdog Timer time-out
0
1
1
0
Watchdog Timer Reload Upper, High and Low Byte Registers
The Watchdog Timer Reload Upper, High and Low Byte (WDTU, WDTH, WDTL) regis-
ters, shown in Tables 50 through 52, form the 24-bit reload value that is loaded into the
Watchdog Timer when a WDT instruction executes. The 24-bit reload value is
{WDTU[7:0], WDTH[7:0], WDTL[7:0]}. Writing to these registers sets the appropriate
reload value. Reading from these registers returns the current Watchdog Timer count
value.
Caution: The 24-bit WDT reload value must not be set to a value less than 000004H.
Table 50. Watchdog Timer Reload Upper Byte Register (WDTU)
Bit
7
6
5
4
3
2
1
0
Field
WDTU
RESET
1
R/W
R/W*
Address
FF1H
Note: *R/W = Read returns the current WDT count value; write sets the appropriate reload value.
Bit
[7:0]
WDTU
Description
WDT Reload Upper Byte
Most significant byte, bits[23:16] of the 24-bit WDT reload value.
PS019924-0113
PRELIMINARY
Watchdog Timer Control Register