Z8F4822AR020SG Datasheet, PDF (214/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
194
Bit
[4]
BRKLOOP
[3:1]
[0]
RST
Description (Continued)
Breakpoint Loop
This bit determines what action the OCD takes when a BRK instruction is decoded if break-
points are enabled (BRKEN is 1). If this bit is 0, then the DBGMODE bit is automatically set
to 1 and the OCD entered DEBUG Mode. If BRKLOOP is set to 1, then the 
eZ8 CPU loops on the BRK instruction.
0 = BRK instruction sets DBGMODE to 1.
1 = eZ8 CPU loops on BRK instruction.
Reserved
These bits are reserved and must be programmed to 000.
Reset
Setting this bit to 1 resets the Z8 Encore! XP F64xx Series devices. The devices go through
a normal Power-On Reset sequence with the exception that the On-Chip Debugger is not
reset. This bit is automatically cleared to 0 when the reset finishes.
0 = No effect.
1 = Reset the Z8 Encore! XP F64xx Series device.
OCD Status Register
The OCD Status Register, shown in Table 104, reports status information about the current
state of the debugger and the system.
Table 104. OCD Status Register (OCDSTAT)
Bit
7
6
5
4
3
2
1
0
Field
IDLE
HALT
RPEN
Reserved
RESET
0
R/W
R
Bit
[7]
IDLE
[6]
HALT
Description
CPU Idle
This bit is set if the part is in DEBUG Mode (DBGMODE is 1), or if a BRK instruction occurred
since the last time OCDCTL was written. This can be used to determine if the CPU is running
or if it is idling.
0 = The eZ8 CPU is running.
1 = The eZ8 CPU is either stopped or looping on a BRK instruction.
HALT Mode
0 = The device is not in HALT Mode.
1 = The device is in HALT Mode.
PS019924-0113
PRELIMINARY
On-Chip Debugger Control Register