Z8F4822AR020SG Datasheet, PDF (123/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
103
Bit
[1]
STOP
[0]
LBEN
Description (Continued)
Stop Bit Select
0 = The transmitter sends one stop bit.
1 = The transmitter sends two stop bits.
Loop Back Enable
0 = Normal operation.
1 = All transmitted data is looped back to the receiver.
Table 58. UART Control 1 Register (UxCTL1)
Bit
7
Field
MPMD[1]
RESET
R/W
Address
6
MPEN
5
MPMD[0]
4
3
MPBT DEPOL
0
R/W
F43H and F4BH
2
1
BRGCTL RDAIRQ
0
IREN
Bit
[7,5]
MPMD[1,0]
[6]
MPEN
[4]
MPBT
[3]
DEPOL
Description
MULTIPROCESSOR Mode
If MULTIPROCESSOR (9-Bit) Mode is enabled,
00 = The UART generates an interrupt request on all received bytes (data and address).
01 = The UART generates an interrupt request only on received address bytes.
10 = The UART generates an interrupt request when a received address byte matches the
value stored in the Address Compare Register and on all successive data bytes until
an address mismatch occurs.
11 = The UART generates an interrupt request on all received data bytes for which the most
recent address byte matched the value in the Address Compare Register.
MULTIPROCESSOR (9-bit) Enable
This bit is used to enable MULTIPROCESSOR (9-Bit) Mode.
0 = Disable MULTIPROCESSOR (9-Bit) Mode.
1 = Enable MULTIPROCESSOR (9-Bit) Mode.
MULTIPROCESSOR Bit Transmit
This bit is applicable only when MULTIPROCESSOR (9-Bit) Mode is enabled.
0 = Send a 0 in the multiprocessor bit location of the data stream (9th bit).
1 = Send a 1 in the multiprocessor bit location of the data stream (9th bit).
Driver Enable Polarity
0 = DE signal is Active High.
1 = DE signal is Active Low.
PS019924-0113
PRELIMINARY
UART Control Register Definitions