Z8F4822AR020SG Datasheet, PDF (92/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
72
ister. This operation allows accurate reads of the full 16-bit timer count value while
enabled. When the timers are not enabled, a read from the Timer Low Byte Register
returns the actual value in the counter.
Timer Output Signal Operation
A timer output is a GPIO port pin alternate function. Generally, the timer output is toggled
every time the counter is reloaded.
Timer Control Register Definitions
This section defines the features of the following Timer Control registers.
Timer 0–3 High and Low Byte Registers: see page 72
Timer Reload High and Low Byte Registers: see page 74
Timer 0–3 PWM High and Low Byte Registers: see page 75
Timer 0–3 Control 0 Registers: see page 76
Timer 0–3 Control 1 Registers: see page 77
Timers 0–2 are available in all packages. Timer 3 is only available in 64-, 68- and 80-pin
packages.
Timer 0–3 High and Low Byte Registers
The Timer 0–3 High and Low Byte (TxH and TxL) registers, shown in Tables 39 and 40,
contain the current 16-bit timer count value. When the timer is enabled, a read from TxH
causes the value in TxL to be stored in a temporary holding register. A read from TMRL
always returns this temporary register when the timers are enabled. When the timer is dis-
abled, reads from the TMRL read the register directly.
Writing to the Timer High and Low Byte registers while the timer is enabled is not recom-
mended. There are no temporary holding registers available for write operations, so simul-
taneous 16-bit writes are not possible. If either the Timer High or Low Byte registers are
written during counting, the 8-bit written value is placed in the counter (High or Low
Byte) at the next clock edge. The counter continues counting from the new value.
Timer 3 is unavailable in 44-pin packages.
PS019924-0113
PRELIMINARY
Timer Control Register Definitions