Z8F4822AR020SG Datasheet, PDF (43/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
23
Table 7. Z8 Encore! XP F64xx Series Register File Address Map (Continued)
Address (Hex) Register Description
Timer 2 (continued)
F14
Timer 2 PWM High Byte
F15
Timer 2 PWM Low Byte
F16
Timer 2 Control 0
F17
Timer 2 Control 1
Timer 3 (Unavailable in the 44-Pin Package)
F18
Timer 3 High Byte
F19
Timer 3 Low Byte
F1A
F1B
F1C
F1D
F1E
F1F
20–3F
Timer 3 Reload High Byte
Timer 3 Reload Low Byte
Timer 3 PWM High Byte
Timer 3 PWM Low Byte
Timer 3 Control 0
Timer 3 Control 1
Reserved
UART 0
F40
UART0 Transmit Data
UART0 Receive Data
F41
UART0 Status 0
F42
UART0 Control 0
F43
UART0 Control 1
F44
UART0 Status 1
F45
UART0 Address Compare Register
F46
UART0 Baud Rate High Byte
F47
UART0 Baud Rate Low Byte
UART 1
F48
UART1 Transmit Data
UART1 Receive Data
F49
UART1 Status 0
F4A
UART1 Control 0
F4B
UART1 Control 1
F4C
UART1 Status 1
Note: XX = Undefined.
Mnemonic Reset (Hex)
T2PWMH
00
T2PWML
00
T2CTL0
00
T2CTL1
00
T3H
00
T3L
01
T3RH
FF
T3RL
FF
T3PWMH
00
T3PWML
00
T3CTL0
00
T3CTL1
00
—
XX
U0TXD
U0RXD
U0STAT0
U0CTL0
U0CTL1
U0STAT1
U0ADDR
U0BRH
U0BRL
XX
XX
0000011Xb
00
00
00
00
FF
FF
U1TXD
U1RXD
U1STAT0
U1CTL0
U1CTL1
U1STAT1
XX
XX
0000011Xb
00
00
00
Page
75
75
76
77
72
72
74
74
75
75
76
77
98
99
100
102
102
100
105
105
105
98
99
100
102
102
100
PS019924-0113
PRELIMINARY
Register File Address Map