Z8F4822AR020SG Datasheet, PDF (179/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
159
Bit
[5:4]
[3:0]
ADC_IN
Description (Continued)
Reserved
These bits are reserved and must be programmed to 00.
ADC Analog Input Number
These bits set the number of ADC analog inputs to be used in the continuous update (data
conversion followed by DMA data transfer). The conversion always begins with ADC analog
input 0 and then progresses sequentially through the other selected ADC analog inputs.
0000 = ADC analog input 0 updated.
0001 = ADC analog inputs 0–1 updated.
0010 = ADC analog inputs 0–2 updated.
0011 = ADC analog inputs 0–3 updated.
0100 = ADC analog inputs 0–4 updated.
0101 = ADC analog inputs 0–5 updated.
0110 = ADC analog inputs 0–6 updated.
0111 = ADC analog inputs 0–7 updated.
1000 = ADC analog inputs 0–8 updated.
1001 = ADC analog inputs 0–9 updated.
1010 = ADC analog inputs 0–10 updated.
1011 = ADC analog inputs 0–11 updated.
1100–1111 = Reserved.
DMA_ADC Status Register
The DMA Status Register, shown in Table 86, indicates the DMA channel that generated
the interrupt and the ADC analog input that is currently undergoing conversion. Reads
from this register reset the Interrupt Request Indicator bits (IRQA, IRQ1, and IRQ0) to 0.
Therefore, software interrupt service routines that read this register must process all three
interrupt sources from the DMA.
Table 86. DMA_ADC Status Register (DMAA_STAT)
Bit
7
Field
RESET
R/W
Address
6
5
CADC[3:0]
4
3
Reserved
0
R
FBFH
2
IRQA
1
IRQ1
0
IRQ0
Bit
[7:4]
CADC[3:0]
[3]
Description
Current ADC Analog Input
This field identifies the Analog Input that the ADC is currently converting.
Reserved
This bit is reserved and must be programmed to 0.
PS019924-0113
PRELIMINARY
DMA Control Register Definitions