Z8F4822AR020SG Datasheet, PDF (125/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
105
UART Address Compare Register
The UART Address Compare Register, shown in Table 59, stores the multinode network
address of the UART. When the MPMD[1] bit of UART Control Register 0 is set, all
incoming address bytes are compared to the value stored in the Address Compare Regis-
ter. Receive interrupts and RDA assertions only occur in the event of a match.
Table 59. UART Address Compare Register (UxADDR)
Bit
7
6
5
4
3
2
1
0
Field
COMP_ADDR
RESET
0
R/W
R/W
Address
F45H and F4DH
Bit
Description
[7:0]
Compare Address
COMP_ADDR This 8-bit value is compared to the incoming address bytes.
UART Baud Rate High and Low Byte Registers
The UART Baud Rate High and Low Byte registers, shown in Tables 60 and 61, combine
to create a 16-bit baud rate divisor value (BRG[15:0]) that sets the data transmission rate
(baud rate) of the UART. To configure the Baud Rate Generator as a timer with interrupt
on time-out, complete the following procedure:
1. Disable the UART by clearing the REN and TEN bits in the UART Control 0 Register
to 0.
2. Load the appropriate 16-bit count value into the UART Baud Rate High and Low Byte
registers.
3. Enable the Baud Rate Generator timer function and associated interrupt by setting the
BRGCTL bit in the UART Control 1 Register to 1.
When configured as a general-purpose timer, the UART BRG interrupt interval is calcu-
lated using the following equation:
UART BRG Interrupt Intervals = System Clock Period (s)  BRG15:0
PS019924-0113
PRELIMINARY
UART Control Register Definitions