Z8F4822AR020SG Datasheet, PDF (257/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
237
Table 136. eZ8 CPU Instruction Summary (Continued)
Assembly
Mnemonic
DA dst
Symbolic Operation
dst ← DA(dst)
Address
Mode
dst src
R
IR
DEC dst
dst ← dst – 1
R
IR
DECW dst
dst ← dst – 1
RR
IRR
DI
IRQCTL[7] ← 0
DJNZ dst, RA dst ← dst – 1
r
if dst  0
PC ← PC + X
EI
IRQCTL[7] ← 1
HALT
HALT Mode
INC dst
dst ← dst + 1
R
IR
r
INCW dst
dst ← dst + 1
RR
IRET
JP dst
IRR
FLAGS ← @SP
SP ← SP + 1
PC ← @SP
SP ← SP + 2
IRQCTL[7] ← 1
PC ← dst
DA
IRR
JP cc, dst
if cc is true
DA
PC ← dst
JR dst
PC ← PC + X
DA
JR cc, dst
if cc is true
DA
PC ← PC + X
Note: Flags Notation:
* = Value is a function of the result of the operation.
– = Unaffected.
X = Undefined.
0 = Reset to 0.
1 = Set to 1.
Opcode(s)
Flags
Fetch Instr.
(Hex) C Z S V D H Cycles Cycles
40
* * *X–– 2
2
41
2
3
30
–* * *–– 2
2
31
2
3
80
–* * *–– 2
5
81
2
6
8F
–––––– 1
2
0A–FA – – – – – – 2
3
9F
–––––– 1
2
7F
–––––– 1
2
20
–* * *–– 2
2
21
2
3
0E–FE
1
2
A0
–* * *–– 2
5
A1
2
6
BF
****** 1
5
8D
–––––– 3
2
C4
2
3
0D–FD – – – – – – 3
2
8B
–––––– 2
2
0B–FB – – – – – – 2
2
PS019924-0113
PRELIMINARY
eZ8 CPU Instruction Summary