Z8F4822AR020SG Datasheet, PDF (139/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
119
Slave Operation
The SPI block is configured for SLAVE Mode operation by setting the SPIEN bit to 1 and
the MMEN bit to 0 in the SPICTL Register and setting the SSIO bit to 0 in the SPIMODE 
Register. The IRQE, PHASE, CLKPOL, WOR bits in the SPICTL Register and the
NUMBITS field in the SPIMODE Register must be set to be consistent with the other SPI
devices. The STR bit in the SPICTL Register may be used if appropriate to force a start-
up interrupt. The BIRQ bit in the SPICTL Register and the SSV bit in the SPIMODE Reg-
ister are not used in SLAVE Mode. The SPI baud rate generator is not used in SLAVE
Mode so the SPIBRH and SPIBRL registers need not be initialized.
If the slave has data to send to the master, the data must be written to the SPIDAT Register
before the transaction starts (first edge of SCK when SS is asserted). If the SPIDAT Regis-
ter is not written prior to the slave transaction, the MISO pin outputs whatever value is
currently in the SPIDAT Register.
Due to the delay resulting from synchronization of the SPI input signals to the internal sys-
tem clock, the maximum SPICLK baud rate that can be supported in SLAVE Mode is the
system clock frequency (X_IN) divided by 8. This rate is controlled by the SPI master.
Error Detection
The SPI contains error detection logic to support SPI communication protocols and recog-
nize when communication errors have occurred. The SPI Status Register indicates when a
data transmission error has been detected.
Overrun (Write Collision)
An overrun error (write collision) indicates that a write to the SPI Data Register was
attempted while a data transfer was in progress (in either MASTER or SLAVE modes). An
overrun sets the OVR bit in the SPI Status Register to 1. Writing a 1 to OVR clears this
error flag. The data register is not altered when a write occurs while data transfer is in
progress.
Mode Fault (Multimaster Collision)
A mode fault indicates when more than one Master is trying to communicate at the same
time (a multimaster collision). The mode fault is detected when the enabled Master’s SS
pin is asserted. A mode fault sets the COL bit in the SPI Status Register to 1. Writing a 1 to
COL clears this error flag.
Slave Mode Abort
In the SLAVE Mode of operation, if the SS pin deasserts before all bits in a character have
been transferred, the transaction is aborted. When this condition occurs, the ABT bit is set
in the SPISTAT Register as well as the IRQ bit (indicating the transaction is complete).
PS019924-0113
PRELIMINARY
Operation