Z8F4822AR020SG Datasheet, PDF (157/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
137
2. Software asserts the TXI bit of the I²C Control Register to enable transmit interrupts.
3. The I²C interrupt asserts because the I²C Data Register is empty.
4. Software responds to the TDRE interrupt by writing the first slave address byte to the
I²C Data Register. The least significant bit must be 0 for the write operation.
5. Software asserts the start bit of the I²C Control Register.
6. The I²C Controller sends the start condition to the I²C slave.
7. The I²C Controller loads the I²C Shift Register with the contents of the I²C Data Reg-
ister.
8. After one bit of address is shifted out by the SDA signal, the transmit interrupt is
asserted.
9. Software responds by writing the second byte of address into the contents of the I²C
Data Register.
10. The I²C Controller shifts the rest of the first byte of address and write bit out the SDA
signal.
11. If the I²C slave acknowledges the first address byte by pulling the SDA signal Low
during the next High period of SCL, the I²C Controller sets the ACK bit in the I²C
Status Register. Continue with Step 12.

If the slave does not acknowledge the first address byte, the I²C Controller sets the
NCKI bit and clears the ACK bit in the I²C Status Register. Software responds to the
Not Acknowledge interrupt by setting the stop and flush bits and clearing the TXI bit.
The I²C Controller sends the stop condition on the bus and clears the stop and NCKI
bits. The transaction is complete (ignore the following steps).
12. The I²C Controller loads the I²C Shift Register with the contents of the I²C Data Reg-
ister.
13. The I²C Controller shifts the second address byte out the SDA signal. After the first
bit has been sent, the transmit interrupt is asserted.
14. Software responds by writing a data byte to the I²C Data Register.
15. The I²C Controller completes shifting the contents of the shift register on the SDA
signal.
16. If the I²C slave sends an acknowledge by pulling the SDA signal Low during the next
High period of SCL, the I²C Controller sets the ACK bit in the I²C Status Register.
Continue with Step 17.

If the slave does not acknowledge the second address byte or one of the data bytes, the
I²C Controller sets the NCKI bit and clears the ACK bit in the I²C Status Register.
Software responds to the Not Acknowledge interrupt by setting the stop and flush bits
and clearing the TXI bit. The I²C Controller sends the stop condition on the bus and
PS019924-0113
PRELIMINARY
Operation