Z8F4822AR020SG Datasheet, PDF (102/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
82
STOP Mode. For more information about Stop Mode Recovery, see the Reset and Stop
Mode Recovery chapter on page 28.
If interrupts are enabled, following completion of the Stop Mode Recovery the eZ8 CPU
responds to the interrupt request by fetching the Watchdog Timer interrupt vector and exe-
cuting code from the vector address.
WDT Reset in Normal Operation
If configured to generate a Reset when a time-out occurs, the Watchdog Timer forces the
device into the Reset state. The WDT status bit in the Watchdog Timer Control Register is
set to 1. For more information about Reset, see the Reset and Stop Mode Recovery chapter
on page 28.
WDT Reset in STOP Mode
If enabled in STOP Mode and configured to generate a Reset when a time-out occurs and
the device is in STOP Mode, the Watchdog Timer initiates a Stop Mode Recovery. Both
the WDT status bit and the stop bit in the Watchdog Timer Control Register are set to 1
following WDT time-out in STOP Mode. Default operation is for the WDT and its RC
oscillator to be enabled during STOP Mode.
WDT RC Disable in STOP Mode
To minimize power consumption in STOP Mode, the WDT and its RC oscillator can be
disabled in STOP Mode. The following sequence configures the WDT to be disabled
when the Z8 Encore! XP F64xx Series devices enter STOP Mode following execution of a
stop instruction:
1. Write 55H to the Watchdog Timer Control Register (WDTCTL).
2. Write AAH to the Watchdog Timer Control Register (WDTCTL).
3. Write 81H to the Watchdog Timer Control Register (WDTCTL) to configure the WDT
and its oscillator to be disabled during STOP Mode. Alternatively, write 00H to the
Watchdog Timer Control Register (WDTCTL) as the third step in this sequence to
reconfigure the WDT and its oscillator to be enabled during STOP Mode.
This sequence only affects WDT operation in STOP Mode.
Watchdog Timer Reload Unlock Sequence
Writing the unlock sequence to the Watchdog Timer (WDTCTL) Control Register address
unlocks the three Watchdog Timer Reload Byte registers (WDTU, WDTH, and WDTL) to
allow changes to the time-out period. These write operations to the WDTCTL Register
address produce no effect on the bits in the WDTCTL Register. The locking mechanism
prevents spurious writes to the Reload registers. Observe the following procedure to
PS019924-0113
PRELIMINARY
Operation