Z8F4822AR020SG Datasheet, PDF (159/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
139
set in the Status Register, ACK bit is cleared). Software responds to the Not Acknowl-
edge interrupt by setting the stop bit and clearing the TXI bit. The I²C Controller
sends the stop condition on the bus and clears the stop and NCKI bits. The transaction
is complete (ignore the following steps).
7. The I²C Controller shifts in the byte of data from the I²C slave on the SDA signal. The
I²C Controller sends a Not Acknowledge to the I²C slave if the NAK bit is set (last
byte), else it sends an Acknowledge.
8. The I²C Controller asserts the receive interrupt (RDRF bit set in the Status Register).
9. Software responds by reading the I²C Data Register which clears the RDRF bit. If
there is only one more byte to receive, set the NAK bit of the I²C Control Register.
10. If there are more bytes to transfer, return to Step 7.
11. After the last byte is shifted in, a Not Acknowledge interrupt is generated by the I²C
Controller.
12. Software responds by setting the stop bit of the I²C Control Register.
13. A stop condition is sent to the I²C slave, the stop and NCKI bits are cleared.
Read Transaction with a 10-Bit Address
Figure 33 displays the read transaction format for a 10-bit addressed slave. The shaded
regions indicate data transferred from the I²C Controller to slaves and unshaded regions
indicate data transferred from the slaves to the I²C Controller.
S
Slave Address
1st 7 bits
W=0
A
Slave Address
2nd Byte
A
S
Slave Address
1st 7 bits
R=1
A
Data
A
Data
AP
Figure 33. Receive Data Format for a 10-Bit Addressed Slave
The first seven bits transmitted in the first byte are 11110XX. The two (XX) bits are the two
most significant bits of the 10-bit address. The lowest bit of the first byte transferred is the
write control bit.
Observe the following procedure for the data transfer for a read operation to a 10-bit
addressed slave:
1. Software writes 11110B followed by the two address bits and a 0 (write) to the I²C
Data Register.
2. Software asserts the start and TXI bits of the I²C Control Register.
3. The I²C Controller sends the Start condition.
4. The I²C Controller loads the I²C Shift Register with the contents of the I²C Data Reg-
ister.
PS019924-0113
PRELIMINARY
Operation