Z8F4822AR020SG Datasheet, PDF (136/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
116
Serial Clock
The Serial Clock (SCK) synchronizes data movement both in and out of the device
through its MOSI and MISO pins. In MASTER Mode, the SPI’s Baud Rate Generator cre-
ates the serial clock. The Master drives the serial clock out its own SCK pin to the Slave’s
SCK pin. When the SPI is configured as a Slave, the SCK pin is an input and the clock sig-
nal from the Master synchronizes the data transfer between the Master and Slave devices.
Slave devices ignore the SCK signal, unless the SS pin is asserted. When configured as a
slave, the SPI block requires a minimum SCK period of greater than or equal to 8 times
the system (X_IN) clock period.
The Master and Slave are each capable of exchanging a character of data during a
sequence of NUMBITS clock cycles (see the NUMBITS field in the SPI Mode Register
section on page 125). In both Master and Slave SPI devices, data is shifted on one edge of
the SCK and is sampled on the opposite edge where data is stable. Edge polarity is deter-
mined by the SPI phase and polarity control.
Slave Select
The active Low Slave Select (SS) input signal selects a Slave SPI device. SS must be Low
prior to all data communication to and from the Slave device. SS must stay Low for the
full duration of each character transferred. The SS signal may stay Low during the transfer
of multiple characters or may deassert between each character.
When the SPI is configured as the only Master in an SPI system, the SS pin can be set as
either an input or an output. Other GPIO output pins can also be employed to select exter-
nal SPI Slave devices.
When the SPI is configured as one Master in a multimaster SPI system, the SS pin must be
set as an input. The SS input signal on the Master must be High. If the SS signal goes Low
(indicating another Master is driving the SPI bus), a collision error flag is set in the SPI
Status Register.
SPI Clock Phase and Polarity Control
The SPI supports four combinations of serial clock phase and polarity using two bits in the
SPI Control Register. The clock polarity bit, CLKPOL, selects an active high or active
Low clock and has no effect on the transfer format. Table 63 lists the SPI Clock Phase and
Polarity Operation parameters. The clock phase bit, PHASE, selects one of two fundamen-
tally different transfer formats. For proper data transmission, the clock phase and polarity
must be identical for the SPI Master and the SPI Slave. The Master always places data on
the MOSI line a half-cycle before the receive clock edge (SCK signal), in order for the
Slave to latch the data.
PS019924-0113
PRELIMINARY
Operation