Z8F4822AR020SG Datasheet, PDF (143/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
123
Bit
Description (Continued)
[4]
PHASE
Phase Select
Sets the phase relationship of the data to the clock. For more information about operation of
the PHASE bit, see the SPI Clock Phase and Polarity Control section on page 116.
[3]
Clock Polarity
CLKPOL 0 = SCK idles Low (0).
1 = SCK idle High (1).
[2]
WOR
Wire-OR (OPEN-DRAIN) Mode Enabled
0 = SPI signal pins not configured for open-drain.
1 = All four SPI signal pins (SCK, SS, MISO, MOSI) configured for open-drain function. This
setting is typically used for multimaster and/or multislave configurations.
[1]
MMEN
SPI Master Mode Enable
0 = SPI configured in SLAVE Mode.
1 = SPI configured in MASTER Mode.
[0]
SPIEN
SPI Enable
0 = SPI disabled.
1 = SPI enabled.
SPI Status Register
The SPI Status Register, shown in Table 66, indicates the current state of the SPI. All bits
revert to their reset state if the SPIEN bit in the SPICTL Register = 0.
Table 66. SPI Status Register (SPISTAT)
Bit
7
6
5
4
3
2
Field
IRQ
OVR
COL
ABT
Reserved
RESET
0
R/W
R/W*
Address
F62H
Note: R/W* = Read access. Write a 1 to clear the bit to 0.
1
TXST
R
0
SLAS
1
Bit
[7]
IRQ
[6]
OVR
Description
Interrupt Request
If SPIEN = 1, this bit is set if the STR bit in the SPICTL Register is set, or upon completion of
an SPI master or slave transaction. This bit does not set if SPIEN = 0 and the SPI Baud Rate
Generator is used as a timer to generate the SPI interrupt.
0 = No SPI interrupt request pending.
1 = SPI interrupt request is pending.
Overrun
0 = An overrun error has not occurred.
1 = An overrun error has been detected.
PS019924-0113
PRELIMINARY
SPI Control Register Definitions